1. Field of Invention
The present disclosure relates to a package and a manufacturing method thereof. More particularly, the present disclosure relates to a chip package and a manufacturing method thereof.
2. Description of Related Art
Along the evolution in the manufacturing technology of the semiconductor devices, the functional density of the semiconductor devices has increased with the decrease of device sizes to achieve higher integration density of the semiconductor devices. Because the improvement of the integration density of the semiconductor devices, the semiconductor industry has experienced rapid growth. As a result, the demands to the packaging technology are becoming severe under the condition of decrease in size and increase in density of the semiconductor devices. In recent years, the demands to the smaller electronic devices have increased, and innovative packaging technology is required for the semiconductor chip.
Stereoscopic semiconductor chip package technology is an effective choice to further decrease a physical size of a semiconductor chip package. In the stereoscopic semiconductor chip package, the semiconductor chips are stacked vertically, and through-silicon via (TSV) technology is applied to achieve electrically connection between these semiconductor chips. Therefore, the wires between the chips are shortened, and the device sizes are reduced. The stereoscopic semiconductor chip package technology is able to integrate semiconductor chips with different functionalities, and thereby effectively increasing efficiency of the products, reducing the volumes, and achieving higher integration density. In other words, the stereoscopic semiconductor chip package technology is able to form higher integration density in smaller form factors, so as to obtain the semiconductor chip package having multi-functionality and high efficiency. Generally, a stereoscopic semiconductor chip package may include a semiconductor chip, an interposer having through-silicon vias and other substrates. The semiconductor chip is adhered at one side of the interposer by solder bumps, which provides electrical connection between the semiconductor chip and the interposer. The other side of the interposer is electrically connected to a printed circuit board or other interposers via solder balls. The through-silicon vias integrate the semiconductor chip and the printed circuit board on opposite sides of the interposer, which the printed circuit board may be substituted by other integrated circuit chips.
Among the integration of the semiconductor chip and the interposer, the solder bumps are formed of specific alloys, and an eutectic bonding method is applied to perform transition between metal phases. The eutectic bonding method is a special diffusion bonding to make the alloys mix and diffuse under a melting point lower than that of any solutes. Thus, a metal interface bonding is formed between the semiconductor chip and the interposer at a lower temperature of about 400° C. to 500° C. However, when performing the eutectic bonding method, the demands on controlling parameters of an annealing process is high, such as temperature and heat cycles, so that small variations of the process easily make solder bumps generate mechanical stress to affect the metal interface bonding. As a result, problems of failure connection and fracture may easily occur on the solder bumps between the semiconductor chip and the interposer. Therefore, a more reliable chip package suitable for mass production and a manufacturing method thereof is one of the important researches in the present semiconductor chip package technology.